A tunable multi-timescale Indium-Gallium-Zinc-Oxide thin-film transistor neuron towards hybrid solutions for spiking neuromorphic applications

Spiking neural network algorithms require fine-tuned neuromorphic hardware to increase their effectiveness. Such hardware, mainly digital, is typically built on mature silicon nodes. Future artificial intelligence applications will demand the execution of tasks with increasing complexity and over timescales spanning several decades. The multi-timescale requirements for certain tasks cannot be attained effectively enough through the existing silicon-based solutions. Indium-Gallium-Zinc-Oxide thin-film transistors can alleviate the timescale-related shortcomings of silicon platforms thanks to their bellow atto-ampere leakage currents. These small currents enable wide timescale ranges, far beyond what has been feasible through various emerging technologies. Here we have estimated and exploited these low leakage currents to create a multi-timescale neuron that integrates information spanning a range of 7 orders of magnitude and assessed its advantages in larger networks. The multi-timescale ability of this neuron can be utilized together with silicon to create hybrid spiking neural networks capable of effectively executing more complex tasks than their single-technology counterparts.

During normal capacitor discharge, transistor Mreset needs to be turned OFF completely, without any undesired leakage current, to guarantee it will not distort the characterization of the digitally-controlled leakage current source discharging capacitor C. For this, its VGS voltage has to be set sufficiently negative, like VGS ≤ -1.5V.Transistor Mreset is turned OFF by setting its gate voltage Vdelay = 0V.Consequently, its source voltage VC ≥ 1.5V.Since VC will be oscillating between VTOP and VBOTTOM, one should set VDD to guarantee VBOTTOM ≥ 1.5V.
In our measurements, we have typically set VDD = 6V (thus VBOTTOM ≈ 1.5V) and VTOP between 3V and 4.5V.Voltage VC is observed through the simple source-follower circuit shown in Supplementary Fig. 3(b).The nFET is on-chip, while the resistor is connected outside the chip.Ideally, a source follower would require a constant current source (instead of the resistor) to guarantee a constant gate-to-source voltage.Using a resistor will add a modulation to the gate-to-source voltage, making the source follower slightly non-linear.However, by setting Vbb sufficiently negative (Vbb ≤ -2V) with RS ≈100k, its nonlinearity is minimized.This circuit will introduce a voltage shift of approximately 1V from input to output.In our design, we chose N = 11, with Wvj = 10m, Lvj = 1m, Whj = 5m, Lhj = 4.55m, for j = 0, … 12, and Wv13 = Lv13 = 5m.We picked intentionally an excessive number of branches to reach the technology limit of minimum leakage currents.In practice, the last branches would drive the limit leakage current we want to find out.
The drains of the vertical transistors are connected to either a sinking node Vsink or to the capacitor node VC, through digital control signals <j>.Only one branch will be connected to node VC, while the rest will be connected to node Vsink.Lines <j> are set by a digital decoder, controlled by 4-bit digital word w<0:3>.Since we have picked N=11, ideally, we could select leakage currents scaling them down approximately one per decade.However, secondary effects will result in N > 11, as explained later.
The source voltages of the vertical transistors Vsj will be increasing smoothly from the minimum voltage set externally at Vs0 to a maximum at Vs12.Voltage Vs0 should be set low enough, so that Vs12 guarantees a positive VDS voltage at Mv12 and Mv13.The minimum drain voltage is approximately VBOTTOM.On the other hand, Vs0 should not be too negative, to avoid too high VDS voltages, which could stress the TFT transistors and degrade their very low leakage currents.We normally set Vs0 between 0V and 2V.
For optimum current division between consecutive branches, it is desirable that Vsink = VC.However, VC will be oscillating between VTOP and VBOTTOM.As a compromise, we set Vsink ≈ (VTOP + VBOTTOM)/2.
The fact that source voltages Vsj increase with j makes that vertical transistors Mvj, which operate in saturation as current sources, will have larger VDS voltages for smaller j, thus suffering from larger Early Voltage Effect.Therefore, for smaller j, vertical transistors will drive a slightly larger current than expected, leaving a smaller than expected current for the subsequent branches.This will have the secondary effect of resulting in a current ratio Ij/Ij+1 greater than N.